Backside power and PowerVia integration
Intel’s Technology Roadmap Day highlighted a 3nm RibbonFET process that combines backside power delivery with its PowerVia architecture to reduce IR drop by 25% compared with Intel 18A. Source The company says RibbonFET transistors will now support adaptive gate-all-around configurations, enabling foundry clients to tune drive currents for AI and networking workloads without redesigning entire libraries.
Intel also committed to delivering co-optimized reference flows with Synopsys and Cadence by mid-2026. Those partnerships are meant to keep pace with customers exploring custom accelerators, including the teams we profiled while covering open silicon coalitions. See the open silicon push
Packaging upgrades for AI workloads
Packaging remains a focal point. Intel’s Foveros Omni stack gains an AI Bridge interposer that supports 3 TB/s die-to-die bandwidth. The company is marketing the configuration toward cloud providers seeking to mix CPU, GPU, and AI tiles across a single package. Source Intel expects high-volume manufacturing of the 3nm node to start at its Ohio fab complex, which recently passed key construction milestones. Source
What customers should monitor
Foundry customers should evaluate how RibbonFET design kits align with existing IP blocks, paying attention to electromigration rules introduced with backside power. Procurement teams need to track substrate availability, especially if they rely on advanced glass carriers. As Intel competes with TSMC and Samsung on advanced nodes, chip designers should revisit diversification strategies and study how energy-efficient data center goals may influence packaging selections. Weigh sustainability metrics